The present invention generally relates to power mesh schemes for flip chip packages, and more specifically relates to a power mesh scheme which incorporates a donut mesh structure.
In Flip Chip packages, often a center region is covered by very strong power meshes. With such a structure, often voltage drops around the comers and edges of the die are too great. Voltage drops cause decreased performance of the chip. Hence, it is advantageous to design a chip such that voltage drops are not too great.
In an attempt to solve the problem, present flip chip power mesh schemes are being designed such that full horizontal and vertical meshes are filled on redistribution layers, i.e., on the R-1 and R-2 layers. This type of arrangement is shown in FIG. 1. Such an arrangement keeps voltage drops reasonable, but such an arrangement results in many routing resources being used for constructing the power meshes. In FIG. 1, xe2x80x9c4+1+2RFxe2x80x9d refers to a multiple layer design which includes four thin layers, one thicker layer, and two very thick, distribution layers (R1 and R2). Likewise, xe2x80x9c6+1+2RFxe2x80x9d refers to a design which includes six thin layers, one thicker layer, and two very thick, distribution layers, and xe2x80x9c5+1+2RFxe2x80x9d refers to a multiple layer design which includes five thin layers, one thicker layer, and two very thick, distribution layers (where xe2x80x9cFxe2x80x9d refers to Flip Chip in each instance).
The present invention is directed at saving power routing resources without reducing power performance of the chip.
A general object of an embodiment of the present invention is to provide a multiple layer mesh design which includes a donut mesh.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which generally surrounds an open area or hole.
The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. For example, in a stack having an even number of routing layers, the vertical mesh will be on the top layer and the horizontal mesh (with hole) will be on the next layer going down. In a stack having an odd number of routing layers, the horizontal mesh (with hole) will be on the top layer and the vertical mesh will be on the next layer going down. For example, in a five metal layer design (i.e., a design with four thin layers, a thicker layer and a very thick layer, e.g., a redistribution layer), the layer with the horizontal mesh (and hole) is preferably on m5 and the vertical mesh is on m4.
The vertical mesh may be full or may also be a donut mesh. Providing a full vertical mesh guarantees a cross to an m1 power rail at each 200 micrometers. The donut mesh, i.e., layer with horizontal mesh surrounding a hole, supplies power around the edges of a die, and routing resources of the center region (i.e., proximate the hole) are saved.
Preferably, a scheme which includes a vertical donut mesh is used in designs with two R layers, where the upper R is used exclusively by Flip Chip, and the lower R is available in the center, and only the periphery is used by Flip Chip. In such case, preferably holes or open areas are provided in both meshes, and the lower R includes a vertical mesh at its center. Hence, donut meshes exist on xe2x80x9c+1xe2x80x9d (the thick layer) and the top-most thin layer, and the R1 layer has a vertical mesh in the center region.